The present invention concerns the determination of the location of splits in the ground plane and power plane of a printed circuit board in order to minimize radio frequency noise and to minimize the potential of electrostatic discharge to damage components on the printed circuit board.
When designing a printed circuit (PC) board for electromagnetic compatibility, it is often difficult to predict how the ground plane and/or the power plane should be split in order to minimize radio frequency noise and to minimize the potential of electrostatic discharge to damage components on the printed circuit board. This problem is particularly acute in the design of interface cards such as those used to interface a computer system to a local area network (LAN) where, often, an LAN input/output (I/O) driver is placed on the same integrated circuit (IC) as an LAN clock source. In such cases the locations for plane splits are usually determined by experimentation.
In the prior art, experimental results are obtained, for example, by generating multiple versions of the PC board, each with a different splitting of the plane. This, however, tends to be very costly.